Multilayer Thick Film Circuits — Design Rules Every Engineer Should Know

Single layer thick film circuits have a routing density ceiling. When your design pushes against that ceiling — when conductor crossovers become unavoidable and component density demands more interconnect layers than a single surface can support — multilayer thick film construction is the answer.

But moving from single layer to multilayer is not simply a matter of printing more layers on top of each other. It introduces a set of manufacturing realities that, if not understood at the design stage, will cost you yield, reliability, and schedule.

Here are the design rules that matter.

What Multilayer Thick Film Actually Is

A multilayer thick film circuit is built by sequentially printing and firing conductor layers separated by printed dielectric layers on a ceramic substrate. Each conductor layer carries signals or power in a defined pattern. Each dielectric layer electrically isolates adjacent conductor layers from each other. Vias — openings filled with conductor paste — provide vertical interconnects between layers.

The key word is sequential. Every layer is printed, dried, and fired before the next layer is applied. A circuit with four conductor layers and three dielectric layers goes through the furnace seven times. Every firing cycle matters.

Design Rule 1 — Layer Stack Symmetry

Substrate warpage is the most common manufacturing problem in multilayer thick film. It results from the accumulated stress of multiple firing cycles combined with the differential thermal expansion between layers.

The most effective design-level control for warpage is layer stack symmetry. A symmetric stack — where the number and thickness of layers above the substrate centerline mirrors those below — distributes thermal stress evenly and minimizes the net bending moment that causes warpage.

In practice this means planning your layer stack from the beginning of the design process rather than adding layers as routing demands grow. A stack designed for symmetry from the start will yield significantly better than one where layers were added reactively.

For asymmetric stacks that cannot be avoided — such as circuits with conductor layers on one side only — specifying a slightly thicker substrate compensates partially for the asymmetric stress.

Design Rule 2 — Via Size and Registration

Vias are the vertical interconnects that make multilayer routing possible. They are also one of the primary yield drivers in multilayer thick film manufacturing.

The minimum practical via diameter for standard thick film processes is 8 to 10 mils. Smaller vias are possible but require tighter process controls and carry higher risk of incomplete fill — a via that appears closed on the surface but has a void in its center that creates a high-resistance or open interconnect in service.

Registration — the alignment of each successive layer to those below — determines how reliably your vias connect. Standard thick film screen printing achieves layer-to-layer registration of approximately ±1 to ±2 mils. Your via land pads must be sized to accommodate this registration tolerance.

A via with an 8 mil diameter needs a land pad of at least 14 to 16 mils to ensure the via remains within the pad boundary across the full registration tolerance range. Designers who size land pads to the via diameter without adding registration margin will see intermittent connection failures that are difficult to reproduce and expensive to diagnose.

Design Rule 3 — Dielectric Layer Coverage and Thickness

The dielectric layer performs two functions — electrical isolation between conductor layers and mechanical support for the conductor layer above it. Both functions depend on dielectric coverage and thickness being controlled within tight limits.

Dielectric layers must fully cover the conductor layer below with no pinholes or voids. A single pinhole through a dielectric layer creates an interlayer short that is invisible at ambient temperature and may only manifest intermittently under thermal stress. Screen-printed dielectrics typically require two print-fire cycles per layer to achieve void-free coverage — a single print is rarely sufficient for reliable isolation.

Dielectric thickness also determines interlayer capacitance. For circuits where interlayer capacitance is a design parameter — RF circuits, high-speed digital, precision analog — the dielectric thickness must be specified and controlled explicitly rather than left as a process default.

Design Rule 4 — Conductor Layer Thickness Buildup

Each conductor layer adds physical height to the circuit stack. On a multilayer circuit with four conductor layers and three dielectric layers the total stack height above the ceramic surface can reach 50 to 80 microns depending on layer thicknesses.

This buildup affects the planarity of the top surface — which matters for any component that must be mounted flat against the circuit, for wire bonding where the bonding tool must approach the surface at a controlled angle, and for lid sealing on hermetic packages where the sealing surface must be flat within tight tolerances.

Managing conductor and dielectric layer thicknesses individually so the cumulative stack height stays within the planarity requirements of your assembly process is a discipline that begins at the design stage.

Design Rule 5 — Resistor Placement in Multilayer Designs

Resistors in multilayer thick film circuits are typically printed on the top conductor layer — the last layer fired. This gives the laser trimming operation direct access to the resistor surface.

Resistors buried beneath dielectric layers cannot be laser trimmed after the dielectric is applied. If your design places resistors on inner layers — which is occasionally necessary for density reasons — those resistors must be trimmed before the overlying dielectric is printed, and their resistance values will shift slightly during subsequent firing cycles. This shift must be characterized and compensated in the initial trim target.

The practical design rule is simple — place resistors on the top layer wherever possible. When inner layer resistors are unavoidable, characterize the resistance shift through subsequent firing cycles and adjust your trim targets accordingly.

Design Rule 6 — Thermal Budget Management

Every firing cycle consumes thermal budget. The glass frit in conductor and resistor pastes flows during firing, bonds to the substrate, and solidifies. Repeated firing cycles cause previously fired layers to experience multiple thermal excursions above the glass transition temperature of the frit system.

The cumulative effect is measurable. Conductor adhesion — measured as peel strength — degrades with each successive firing cycle. Resistor values drift. In paste systems not designed for multiple firings these effects can be significant.

The mitigation is twofold — specify paste systems rated for the number of firing cycles your layer count requires, and minimize unnecessary firing cycles by maximizing the number of layers printed and dried before each firing event where process constraints allow.

Multilayer thick film design is a discipline that rewards engineers who understand manufacturing realities. Layer stack symmetry prevents warpage. Adequate via land pads ensure interconnect reliability. Double-printed dielectrics prevent interlayer shorts. Resistors on the top layer enable accurate laser trimming.

None of these rules are arbitrary. Each one reflects a failure mode that occurs predictably when the rule is ignored. Apply them from the beginning of your design and your multilayer thick film circuit will yield well, perform reliably, and survive the thermal and mechanical demands of its operating environment.

CMS Circuits manufactures complex multilayer thick film circuits for aerospace, defense, medical, and space applications. ISO 9001 · AS9100 Rev D · ISO 13485 · ITAR Registered. Murrieta, California.

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